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R8C/26 Group, R8C/27 Group
SINGLE-CHIP 16-BIT CMOS MCU
REJ03B0168-0130 Rev.1.30 May 25, 2007
1.
Overview
These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C/Tiny Series CPU core, and are packaged in a 32-pin molded-plastic LQFP. It implements sophisticated instructions for a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Furthermore, the R8C/27 Group has on-chip data flash (1 KB x 2 blocks). The difference between the R8C/26 Group and R8C/27 Group is only the presence or absence of data flash. Their peripheral functions are the same.
1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer products, automotive, etc.
J and K versions are under development. Specifications may be changed without prior notice.
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 1 of 69
R8C/26 Group, R8C/27 Group
1. Overview
1.2
Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/26Group and Table 1.2 outlines the Functions and Specifications for R8C/27 Group. Table 1.1
CPU
Functions and Specifications for R8C/26Group
Item Number of fundamental instructions Minimum instruction execution time Operating mode Address space Memory capacity Ports LED drive ports Timers Specification 89 instructions 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version) 62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version) Single-chip 1 Mbyte Refer to Table 1.3 Product Information for R8C/26 Group I/O ports: 25 pins, Input port: 3 pins I/O ports: 8 pins (N, D version) Timer RA: 8 bits x 1 channel Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RC: 16 bits x 1 channel (Input capture and output compare circuits) Timer RE: With real-time clock and compare match function (For J, K version, compare match function only.) 2 channels (UART0, UART1) Clock synchronous serial I/O, UART 1 channel I2C bus Interface(1) Clock synchronous serial I/O with chip select Hardware LIN: 1 channel (timer RA, UART0) 10-bit A/D converter: 1 circuit, 12 channels 15 bits x 1 channel (with prescaler) Start-on-reset selectable Internal: 15 sources, External: 4 sources, Software: 4 sources, Priority levels: 7 levels 3 circuits * XIN clock generation circuit (with on-chip feedback resistor) * On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has a frequency adjustment function * XCIN clock generation circuit (32 kHz) (N, D version) * Real-time clock (timer RE) (N, D version) XIN clock oscillation stop detection function On-chip On-chip VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version) VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version) VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version) Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 2.0 A (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz) Typ. 0.7 A (VCC = 3.0 V, stop mode) VCC = 2.7 to 5.5 V 100 times -20 to 85C (N version) -40 to 85C (D, J version)(2), -40 to 125C (K version)(2) 32-pin molded-plastic LQFP
Peripheral Functions
Serial interfaces Clock synchronous serial interface LIN module A/D converter Watchdog timer Interrupts Clock generation circuits
Electrical Characteristics
Oscillation-stopped detector Voltage detection circuit Power-on reset circuit Supply voltage
Current consumption (N, D version) Flash Memory Programming and erasure voltage Programming and erasure endurance Operating Ambient Temperature
Package NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Specify the D, K version if D, K version functions are to be used.
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 2 of 69
R8C/26 Group, R8C/27 Group
1. Overview
Table 1.2
CPU
Functions and Specifications for R8C/27 Group
Item Specification Number of fundamental 89 instructions instructions Minimum instruction 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version) execution time 62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version) Operating mode Single-chip Address space 1 Mbyte Memory capacity Refer to Table 1.4 Product Information of R8C/27 Group Peripheral Ports I/O ports: 25 pins, Input port: 3 pins Functions LED drive ports I/O ports: 8 pins (N, D version) Timers Timer RA: 8 bits x 1 channel Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RC: 16 bits x 1 channel (Input capture and output compare circuits) Timer RE: With real-time clock and compare match function (For J, K version, compare match function only.) Serial interfaces 2 channels (UART0, UART1) Clock synchronous serial I/O, UART Clock synchronous 1 channel serial interface I2C bus Interface(1) Clock synchronous serial I/O with chip select LIN module Hardware LIN: 1 channel (timer RA, UART0) A/D converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog timer 15 bits x 1 channel (with prescaler) Start-on-reset selectable Interrupts Internal: 15 sources, External: 4 sources, Software: 4 sources, Priority levels: 7 levels Clock generation 3 circuits circuits * XIN clock generation circuit (with on-chip feedback resistor) * On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has a frequency adjustment function * XCIN clock generation circuit (32 kHz) (N, D version) * Real-time clock (timer RE) (N, D version) Oscillation-stopped XIN clock oscillation stop detection function detector Voltage detection circuit On-chip Power-on reset circuit On-chip Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version) Characteristics VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version) VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version) Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz) (N, D version) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 2.0 A (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz) Typ. 0.7 A (VCC = 3.0 V, stop mode) Flash Memory Programming and VCC = 2.7 to 5.5 V erasure voltage Programming and 10,000 times (data flash) erasure endurance 1,000 times (program ROM) Operating Ambient Temperature -20 to 85C (N version) -40 to 85C (D, J version)(2), -40 to 125C (K version)(2) Package 32-pin molded-plastic LQFP NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Specify the D, K version if D, K version functions are to be used.
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R8C/26 Group, R8C/27 Group
1. Overview
1.3
Block Diagram
Figure 1.1 shows a Block Diagram.
8
8
6
1
3
2
I/O ports
Port P0
Port P1
Port P3
Port P4
Port P5
Peripheral functions
A/D converter (10 bits x 12 channels) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-Speed on-chip oscillator XCIN-XCOUT(3)
Timers Timer RA (8 bits) Timer RB (8 bits) Timer RC (16 bits x 1 channel) Timer RE (8 bits)
UART or clock synchronous serial I/O (8 bits x 2 channels)
I2C bus interface or clock synchronous serial I/O with chip select (8 bits x 1 channel)
LIN module (1 channel)
Watchdog timer (15 bits)
R8C/Tiny Series CPU core
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
ROM(1)
RAM(2)
Multiplier
NOTES: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. 3. XCIN, XCOUT can be used only for N or D version.
Figure 1.1
Block Diagram
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 4 of 69
R8C/26 Group, R8C/27 Group
1. Overview
1.4
Product Information
Table 1.3 lists Product Information for R8C/26 Group and Table 1.4 lists Product Information for R8C/27 Group. Table 1.3 Product Information for R8C/26 Group Part No. R5F21262SNFP R5F21264SNFP R5F21265SNFP R5F21266SNFP R5F21262SDFP R5F21264SDFP R5F21265SDFP R5F21266SDFP R5F21264JFP (D) R5F21266JFP (D) R5F21264KFP (D) R5F21266KFP (D) R5F21262SNXXXFP (D) R5F21264SNXXXFP (D) R5F21265SNXXXFP (D) R5F21266SNXXXFP (D) R5F21262SDXXXFP (D) R5F21264SDXXXFP (D) R5F21265SDXXXFP (D) R5F21266SDXXXFP (D) R5F21264JXXXFP (D) R5F21266JXXXFP (D) R5F21264KXXXFP (D) R5F21266KXXXFP (D) ROM Capacity 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 16 Kbytes 32 Kbytes 16 Kbytes 32 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 16 Kbytes 32 Kbytes 16 Kbytes 32 Kbytes RAM Capacity 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 1 Kbyte 1.5 Kbytes 1 Kbyte 1.5 Kbytes 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 1 Kbyte 1.5 Kbytes 1 Kbyte 1.5 Kbytes Package Type PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A N version Current of May. 2007 Remarks
D version
J version(1) K version(1) N version(1) Factory programming product(2)
D version(1)
J version(1) K version(1)
(D): Under development NOTES: 1. These versions are under development. Specifications may be changed without prior notice. 2. The user ROM is programmed before shipment.
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R8C/26 Group, R8C/27 Group
1. Overview
Part No.
R 5 F 21 26 6 S N XXX FP
Package type: FP: PLQP0032GB-A ROM number Classification N: Operating ambient temperature -20C to 85C (N version) D: Operating ambient temperature -40C to 85C (D version) J: Operating ambient temperature -40C to 85C (J version) K: Operating ambient temperature -40C to 125C (K version) S: Low-voltage version (other no symbols) ROM capacity 2: 8 KB 4: 16 KB 5: 24 KB 6: 32 KB R8C/26 Group R8C/Tiny Series Memory type F: Flash memory version Renesas MCU Renesas semiconductor
Figure 1.2
Part Number, Memory Size, and Package of R8C/26 Group
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R8C/26 Group, R8C/27 Group
1. Overview
Table 1.4
Product Information for R8C/27 Group
ROM Capacity Program Data flash ROM 8 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 RAM Capacity 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 1 Kbyte 1.5 Kbytes 1 Kbyte 1.5 Kbytes 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 1 Kbyte 1.5 Kbytes 1 Kbyte 1.5 Kbytes Package Type PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A
Current of May. 2007
Remarks N version
Part No. R5F21272SNFP R5F21274SNFP R5F21275SNFP R5F21276SNFP R5F21272SDFP R5F21274SDFP R5F21275SDFP R5F21276SDFP R5F21274JFP (D) R5F21276JFP (D) R5F21274KFP (D) R5F21276KFP (D) R5F21272SNXXXFP (D) R5F21274SNXXXFP (D) R5F21275SNXXXFP (D) R5F21276SNXXXFP (D) R5F21272SDXXXFP (D) R5F21274SDXXXFP (D) R5F21275SDXXXFP (D) R5F21276SDXXXFP (D) R5F21274JXXXFP (D) R5F21276JXXXFP (D) R5F21274KXXXFP (D) R5F21276KXXXFP (D)
D version
J version(1) K version(1) N version(1) Factory programming product(2) D version(1)
J version(1) K version(1)
(D): Under development NOTES: 1. These versions are under development. Specifications may be changed without prior notice. 2. The user ROM is programmed before shipment.
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R8C/26 Group, R8C/27 Group
1. Overview
Part No. R 5 F 21 27 6 S N XXX FP
Package type: FP: PLQP0032GB-A ROM number Classification N: Operating ambient temperature -20C to 85C (N version) D: Operating ambient temperature -40C to 85C (D version) J: Operating ambient temperature -40C to 85C (J version) K: Operating ambient temperature -40C to 125C (K version) S: Low-voltage version (other no symbols) ROM capacity 2: 8 KB 4: 16 KB 5: 24 KB 6: 32 KB R8C/27 Group R8C/Tiny Series Memory type F: Flash memory version Renesas MCU Renesas semiconductor
Figure 1.3
Part Number, Memory Size, and Package of R8C/27 Group
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Page 8 of 69
R8C/26 Group, R8C/27 Group
1. Overview
1.5
Pin Assignments
Figure 1.4 shows Pin Assignments (Top View).
P1_1/KI1/AN9/TRCIOA/TRCTRG VREF/P4_2 P1_2/KI2/AN10/TRCIOB
P3_4/SDA/SCS/(TRCIOC)(2) P3_3/INT3/SSI/TRCCLK
P1_3/KI3/AN11/(TRBO)
P1_0/KI0/AN8
24 23 22 21 20 19 18 17
P1_4/TXD0
P0_7/AN0 P0_6/AN1 P0_5/AN2/CLK1 P0_4/AN3/TREO P0_3/AN4 P0_2/AN5 P0_1/AN6 P0_0/AN7/(TXD1)(2)
25 26 27 28 29 30 31 32 1
16 15
R8C/26 Group, R8C/27 Group
PLQP0032GB-A (32P6U-A) (top view)
2 3 4 5 6 7 8
14 13 12 11 10 9
P1_5/RXD0/(TRAIO)/(INT1)(2) P1_6/CLK0/(SSI)(2) P5_3/TRCIOC P5_4/TRCIOD P3_1/TRBO P3_6/(TXD1)/(RXD1)/(INT1)(2) P1_7/TRAIO/INT1 P4_5/INT0/(RXD1)(2)
P3_5/SCL/SSCK/(TRCIOD)(2) P3_7/TRAO/SSO/RXD1/(TXD1)(2)
RESET XOUT/XCOUT/P4_7 (1, 3)
VSS/AVSS XIN/XCIN/P4_6 (3)
NOTES: 1. P4_7 is an input-only port. 2. Can be assigned to the pin in parentheses by a program. 3. XCIN, XCOUT can be used only for N or D version. 4. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.4
Pin Assignments (Top View)
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VCC/AVCC
MODE
R8C/26 Group, R8C/27 Group
1. Overview
1.6
Pin Functions
Table 1.5 lists Pin Functions. Table 1.5
Type
Pin Functions
Symbol I/O Type I I I I I O I O I I O I/O O I I I/O O I/O I O I/O I/O I/O I/O I/O I/O I I I/O Description Apply 2.2 V to 5.5 V (J, K version are 2.7 V to 5.5 V) to the VCC pin. Apply 0 V to the VSS pin. Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Input "L" on this pin resets the MCU. Connect this pin to VCC via a resistor. These pins are provided for XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an external clock, input it to the XIN pin and leave the XOUT pin open. These pins are provided for XCIN clock generation circuit I/O. Connect a crystal oscillator between the XCIN and XCOUT pins. To use an external clock, input it to the XCIN pin and leave the XCOUT pin open. INT interrupt input pins Key input interrupt input pins Timer RA output pin Timer RA I/O pin Timer RB output pin External clock input pin External trigger input pin Sharing output-compare output / input-capture input / PWM / PWM2 output pins Timer RE output pin Clock I/O pin Receive data input pin Transmit data output pin Clock I/O pin Data I/O pin Data I/O pin Chip-select signal I/O pin Clock I/O pin Data I/O pin Reference voltage input pin to A/D converter Analog input pins to A/D converter CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. P1_0 to P1_7 also function as LED drive ports. (N, D version) Input-only ports
Power supply input VCC, VSS Analog power supply input Reset input MODE XIN clock input XIN clock output XCIN clock input (N, D version) XCIN clock output (N, D version) INT interrupt input Key input interrupt Timer RA Timer RB Timer RC AVCC, AVSS RESET MODE XIN XOUT XCIN XCOUT INT0, INT1, INT3 KI0 to KI3 TRAO TRAIO TRBO TRCCLK TRCTRG TRCIOA, TRCIOB, TRCIOC, TRCIOD Timer RE Serial interface TREO CLK0, CLK1 RXD0, RXD1 TXD0, TXD1 I2C bus interface SCL SDA Clock synchronous SSI serial I/O with chip SCS select SSCK SSO Reference voltage input A/D converter I/O port VREF AN0 to AN11 P0_0 to P0_7, P1_0 to P1_7, P3_1, P3_3 to P3_7, P4_5, P5_3, P5_4 P4_2, P4_6, P4_7 O: Output
Input port I: Input
I
I/O: Input and output
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R8C/26 Group, R8C/27 Group
1. Overview
Table 1.6
Pin Name Information by Pin Number
I/O Pin Functions for of Peripheral Modules Clock A/D Serial Synchronous I2C bus Timer Interface Serial I/O with Interface Converter Chip Select (1) SSCK SCL (TRCIOD) RXD1/ TRAO SSO (TXD1)(1)
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Control Pin
Port
Interrupt
P3_5 P3_7 RESET XOUT/XCOUT(2) VSS/AVSS XIN/XCIN(2) VCC/AVCC MODE P4_7 P4_6
P4_5 P1_7 P3_6 P3_1 P5_4 P5_3 P1_6 P1_5 P1_4 P1_3 P1_2 VRFF P4_2 P1_1 P1_0 P3_3 P3_4 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0
INT0 INT1 (INT1)(1) TRBO TRCIOD TRCIOC TRAIO
(RXD1)(1) (TXD1)/ (RXD1)(1)
CLK0 (INT1)(1) KI3 KI2 KI1 KI0 INT3 TRCCLK (TRCIOC)(1) (TRAIO)(1) (TRBO) TRCIOB TRCIOA/ TRCTRG RXD0 TXD0
(SSI)(1)
AN11 AN10 AN9 AN8 SSI SCS SDA AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
CLK1 TREO
(TXD1)(1)
NOTES: 1. This can be assigned to the pin in parentheses by a program. 2. XCIN, XCOUT can be used only for N or D version.
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R8C/26 Group, R8C/27 Group
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank.
b31
b15
b8b7
b0
R2 R3
R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers(1)
R2 R3 A0 A1 FB
b19 b15 b0
Address registers(1) Frame base register(1)
INTBH
INTBL
Interrupt table register
The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL.
b19 b0
PC
Program counter
b15
b0
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
U I OBSZDC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit
NOTE: 1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
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R8C/26 Group, R8C/27 Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 to be used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
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R8C/26 Group, R8C/27 Group
2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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R8C/26 Group, R8C/27 Group
3. Memory
3.
3.1
Memory
R8C/26 Group
Figure 3.1 is a Memory Map of R8C/26 Group. The R8C/26 group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special Function Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXh 0FFDCh
Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer/oscillation stop detection/voltage monitor
0YYYYh
Internal ROM (program ROM)
0FFFFh 0FFFFh
(Reserved) (Reserved) Reset
Expanded area
FFFFFh
NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Part Number R5F21262SNFP, R5F21262SDFP, R5F21262SNXXXFP, R5F21262SDXXXFP R5F21264SNFP, R5F21264SDFP, R5F21264JFP, R5F21264KFP, R5F21264SNXXXFP, R5F21264SDXXXFP, R5F21264JXXXFP, R5F21264KXXXFP R5F21265SNFP, R5F21265SDFP R5F21265SNXXXFP, R5F21265SDXXXFP R5F21266SNFP, R5F21266SDFP, R5F21266JFP, R5F21266KFP, R5F21266SNXXXFP, R5F21266SDXXXFP, R5F21266JXXXFP, R5F21266KXXXFP 16 Kbytes 0C000h 1 Kbyte 007FFh Internal ROM Size 8 Kbytes Address 0YYYYh 0E000h Size 512 bytes Internal RAM Address 0XXXXh 005FFh
24 Kbytes
0A000h
1.5 Kbytes
009FFh
32 Kbytes
08000h
1.5 Kbytes
009FFh
Figure 3.1
Memory Map of R8C/26 Group Page 15 of 69
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R8C/26 Group, R8C/27 Group
3. Memory
3.2
R8C/27 Group
Figure 3.2 is a Memory Map of R8C/27 Group. The R8C/27 group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special Function Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXXh 02400h
Internal ROM (data flash)(1)
02BFFh
0FFDCh
Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer/oscillation stop detection/voltage monitor
0YYYYh
Internal ROM (program ROM)
0FFFFh 0FFFFh
(Reserved) (Reserved) Reset
Expanded area
FFFFFh
NOTES: 1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown. 2. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number R5F21272SNFP, R5F21272SDFP, R5F21272SNXXXFP, R5F21272SDXXXFP R5F21274SNFP, R5F21274SDFP, R5F21274JFP, R5F21274KFP, R5F21274SNXXXFP, R5F21274SDXXXFP, R5F21274JXXXFP, R5F21274KXXXFP R5F21275SNFP, R5F21275SDFP, R5F21275SNXXXFP, R5F21275SDXXXFP R5F21276SNFP, R5F21276SDFP, R5F21276JFP, R5F21276KFP, R5F21276SNXXXFP, R5F21276SDXXXFP, R5F21276JXXXFP, R5F21276KXXXFP 32 Kbytes 08000h 1.5 Kbytes 009FFh 24 Kbytes 0A000h 1.5 Kbytes 009FFh Size 8 Kbytes Address 0YYYYh 0E000h Size 512 bytes Internal RAM Address 0XXXXh 005FFh
16 Kbytes
0C000h
1 Kbyte
007FFh
Figure 3.2
Memory Map of R8C/27 Group Page 16 of 69
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R8C/26 Group, R8C/27 Group
4. Special Function Registers (SFRs)
4.
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special function registers. Table 4.1
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch
SFR Information (1)(1)
Register Symbol After reset
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1
PM0 PM1 CM0 CM1
00h 00h 01101000b 00100000b
Protect Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0
PRCR OCD WDTR WDTS WDC RMAD0
00h 00000100b XXh XXh 00X11111b 00h 00h 00h 00h 00h 00h 00h
Address Match Interrupt Enable Register Address Match Interrupt Register 1
AIER RMAD1
Count Source Protection Mode Register
CSPR
00h 10000000b(2)
001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h High-Speed On-Chip Oscillator Control Register 0 0024h High-Speed On-Chip Oscillator Control Register 1 0025h High-Speed On-Chip Oscillator Control Register 2 0026h 0027h 0028h Clock Prescaler Reset Flag 0029h High-Speed On-Chip Oscillator Control Register 4(3) 002Ah 002Bh High-Speed On-Chip Oscillator Control Register 6(3) 002Ch 002Dh 002Eh 002Fh X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The CSPROINI bit in the OFS register is set to 0. 3. In J, K version these regions are reserved. Do not access locations in these regions.
FRA0 FRA1 FRA2
00h When shipping 00h
CPSRF FRA4 FRA6
00h When shipping When shipping
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R8C/26 Group, R8C/27 Group Table 4.2
Address 0030h 0031h 0032h
4. Special Function Registers (SFRs)
SFR Information (2)(1)
Register Voltage Detection Register 1 (2) Voltage Detection Register 2 (2) VCA1 VCA2 Symbol After reset 00001000b * N, D version 00h(3) 00100000b(4) * J, K version 00h(7) 01000000b(8)
0033h 0034h 0035h 0036h
Voltage Monitor 1 Circuit Control Register (5)
VW1C
0037h 0038h 0039h 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 006Fh 0070h 007Fh
Voltage Monitor 2 Circuit Control Register (5) Voltage Monitor 0 Circuit Control Register (6)
VW2C VW0C
* N, D version 00001000b * J, K version 0000X000b(7) 0100X000b(8) 00h 0000X000b(3) 0100X001b(4)
Timer RC Interrupt Control Register
TRCIC
XXXXX000b
Timer RE Interrupt Control Register
TREIC
XXXXX000b
Key Input Interrupt Control Register A/D Conversion Interrupt Control Register SSU / IIC Interrupt Control Register(9) UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer RA Interrupt Control Register Timer RB Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register
KUPIC ADIC SSUIC / IICIC S0TIC S0RIC S1TIC S1RIC TRAIC TRBIC INT1IC INT3IC
XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b
INT0 Interrupt Control Register
INT0IC
XX00X000b
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register. (J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect this register. 3. The LVD0ON bit in the OFS register is set to 1 and hardware reset. 4. Power-on reset, voltage monitor 0 reset or the LVD0ON bit in the OFS register is set to 0, and hardware reset. 5. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3. (J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect b2 and b3. 6. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register. (J, K version) These regions are reserved. Do not access locations in these regions. 7. The LVD1ON bit in the OFS register is set to 1 and hardware reset. 8. Power-on reset, voltage monitor 1 reset, or the LVD1ON bit in the OFS register is set to 0 and hardware reset. 9. Selected by the IICSEL bit in the PMR register.
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R8C/26 Group, R8C/27 Group
4. Special Function Registers (SFRs)
Table 4.3
Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh
SFR Information (3)(1)
Register Symbol After reset
UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register
U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB
00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh
SS Control Register H / IIC bus Control Register 1(2) SS Control Register L / IIC bus Control Register 2(2) SS Mode Register / IIC bus Mode Register(2) SS Enable Register / IIC bus Interrupt Enable Register(2) SS Status Register / IIC bus Status Register(2) SS Mode Register 2 / Slave Address Register(2) SS Transmit Data Register / IIC bus Transmit Data Register(2) SS Receive Data Register / IIC bus Receive Data Register(2)
SSCRH / ICCR1 SSCRL / ICCR2 SSMR / ICMR SSER / ICIER SSSR / ICSR SSMR2 / SAR SSTDR / ICDRT SSRDR / ICDRR
00h 01111101b 00011000b 00h 00h / 0000X000b 00h FFh FFh
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Selected by the IICSEL bit in the PMR register.
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R8C/26 Group, R8C/27 Group
4. Special Function Registers (SFRs)
Table 4.4
Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh
SFR Information (4)(1)
Register A/D Register AD Symbol XXh XXh After reset
A/D Control Register 2 A/D Control Register 0 A/D Control Register 1
ADCON2 ADCON0 ADCON1
00h 00h 00h
Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P3 Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register
P0 P1 PD0 PD1 P3 PD3 P4 P5 PD4 PD5
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
Pin Select Register 1 Pin Select Register 2 Pin Select Register 3 Port Mode Register External Input Enable Register INT Input Filter Select Register Key Input Enable Register Pull-Up Control Register 0 Pull-Up Control Register 1 Port P1 Drive Capacity Control Register(2)
PINSR1 PINSR2 PINSR3 PMR INTEN INTF KIEN PUR0 PUR1 P1DRR
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. In J, K version these regions are reserved. Do not access locations in these regions.
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R8C/26 Group, R8C/27 Group
4. Special Function Registers (SFRs)
Table 4.5
Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh
SFR Information (5)(1)
Register Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR After reset 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h FFh FFh FFh
Timer RE Second Data Register / Counter Data Register Timer RE Minute Data Register / Compare Data Register Timer RE Hour Data Register(2) Timer RE Day of Week Data Register(2) Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Clock Source Select Register Timer RC Mode Register Timer RC Control Register 1 Timer RC Interrupt Enable Register Timer RC Status Register Timer RC I/O Control Register 0 Timer RC I/O Control Register 1 Timer RC Counter Timer RC General Register A Timer RC General Register B Timer RC General Register C Timer RC General Register D Timer RC Control Register 2 Timer RC Digital Filter Function Select Register Timer RC Output Master Enable Register
TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC TRCGRA TRCGRB TRCGRC TRCGRD TRCCR2 TRCDF TRCOER
00h 00h 00h 00h 00h 00h 00001000b 01001000b 00h 01110000b 01110000b 10001000b 10001000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00011111b 00h 01111111b
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. In J, K version these regions are reserved. Do not access locations in these regions.
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R8C/26 Group, R8C/27 Group
4. Special Function Registers (SFRs)
Table 4.6
Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh
SFR Information (6)(1)
Register Symbol After reset
X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
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R8C/26 Group, R8C/27 Group
4. Special Function Registers (SFRs)
Table 4.7
Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh FFFFh
SFR Information (7)(1)
Register Symbol After reset
Flash Memory Control Register 4 Flash Memory Control Register1 Flash Memory Control Register 0
FMR4 FMR1 FMR0
01000000b 1000000Xb 00000001b
Option Function Select Register
OFS
(Note 2)
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
5.
5.1
Electrical Characteristics
N, D Version
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Topr = 25C Condition Rated Value -0.3 to 6.5 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 500 -20 to 85 (N version) / -40 to 85 (D version) -65 to 150 Unit V V V mW C C
Table 5.1
Symbol VCC/AVCC VI VO Pd Topr Tstg
Table 5.2
Symbol VCC/AVCC VSS/AVSS VIH VIL IOH(sum) IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(sum) IOL(peak) IOL(avg) f(XIN)
Recommended Operating Conditions
Parameter Supply voltage Supply voltage Input "H" voltage Input "L" voltage Peak sum output "H" current Average sum output "H" current Peak output "H" current Average output "H" current Conditions Min. 2.2 - 0.8 VCC 0 - - - - - - - - - - - - 0 0 0 0 0 0 0 - - Standard Typ. - 0 - - - - - - - - - - - - - - - - - - - - - 125 - Max. 5.5 - VCC 0.2 VCC -160 -80 -10 -40 -5 -20 160 80 10 40 5 20 20 10 5 70 20 10 5 - Unit V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz kHz MHz MHz MHz kHz
Sum of all pins IOH(peak) Sum of all pins IOH(avg) Except P1_0 to P1_7 P1_0 to P1_7 Except P1_0 to P1_7 P1_0 to P1_7 Sum of all pins IOL(peak)
Peak sum output "L" currents Average sum Sum of all pins IOL(avg) output "L" currents Peak output "L" Except P1_0 to P1_7 currents P1_0 to P1_7 Average output Except P1_0 to P1_7 "L" current P1_0 to P1_7 XIN clock input oscillation frequency
f(XCIN) -
XCIN clock input oscillation frequency System clock OCD2 = 0 XlN clock selected OCD2 = 1 On-chip oscillator clock selected
3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V 2.2 V VCC < 2.7 V 2.2 V VCC 5.5 V 3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V 2.2 V VCC < 2.7 V FRA01 = 0 Low-speed on-chip oscillator clock selected FRA01 = 1 High-speed on-chip oscillator clock selected 3.0 V VCC 5.5 V FRA01 = 1 High-speed on-chip oscillator clock selected 2.7 V VCC 5.5 V FRA01 = 1 High-speed on-chip oscillator clock selected 2.2 V VCC 5.5 V
20
MHz
-
-
10
MHz
-
-
5
MHz
NOTES: 1. VCC = 2.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. The typical values when average output current is 100 ms.
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.3
Symbol - -
A/D Converter Characteristics
Parameter Resolution Absolute accuracy 10-bit mode 8-bit mode 10-bit mode 8-bit mode 10-bit mode 8-bit mode Vref = AVCC AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 3.3 V AD = 10 MHz, Vref = AVCC = 3.3 V AD = 5 MHz, Vref = AVCC = 2.2 V AD = 5 MHz, Vref = AVCC = 2.2 V Vref = AVCC AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 5.0 V 8-bit mode Conditions Standard Min. - - - - - - - 10 3.3 2.8 2.2 0 Vref = AVCC = 2.7 to 5.5 V Vref = AVCC = 2.7 to 5.5 V Vref = AVCC = 2.2 to 5.5 V Vref = AVCC = 2.2 to 5.5 V 0.25 1 0.25 1 Without sample and hold With sample and hold Without sample and hold With sample and hold Typ. - - - - - - - - - - - - - - - - Max. 10 3 2 5 2 5 2 40 - - AVCC AVCC 10 10 5 5 Unit Bits LSB LSB LSB LSB LSB LSB k s s V V MHz MHz MHz MHz
Rladder tconv Vref VIA -
Resistor ladder Conversion time 10-bit mode Reference voltage Analog input voltage(2) A/D operating clock frequency
NOTES: 1. AVCC = 2.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode.
P0 P1 P3 P4 P5 30pF
Figure 5.1
Ports P0, P1, and P3 to P5 Timing Measurement Circuit
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.4
Symbol - - - td(SR-SUS) - - - - - - -
Flash Memory (Program ROM) Electrical Characteristics
Parameter Program/erase endurance(2) Byte program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(7) Ambient temperature = 55C Conditions R8C/26 Group R8C/27 Group Standard Min. 100(3) 1,000(3) - - - 650 0 - 2.7 2.2 0 20 Typ. - - 50 0.4 - - - - - - - - Max. - - 400 9 97+CPU clock x 6 cycles - - 3+CPU clock x 4 cycles 5.5 5.5 60 - Unit times times s s s s ns s V V C year
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied.
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.5
Symbol - - - - - td(SR-SUS) - - - - - - -
Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Parameter Program/erase endurance(2) Byte program time (program/erase endurance 1,000 times) Byte program time (program/erase endurance > 1,000 times) Block erase time (program/erase endurance 1,000 times) Block erase time (program/erase endurance > 1,000 times) Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(9) Ambient temperature = 55 C Conditions Standard Min. 10,000(3) - - - - - 650 0 - 2.7 2.2 -20(8) 20 Typ. - 50 65 0.2 0.3 - - - - - - - - Max. - 400 - 9 - 97+CPU clock x 6 cycles - - 3+CPU clock x 4 cycles 5.5 5.5 85 - Unit times s s s s s s ns s V V C year
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times is the same as that in program ROM. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 8. -40C for D version. 9. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Suspend request (maskable interrupt request)
FMR46
Fixed time Clock-dependent time Access restart
td(SR-SUS)
Figure 5.2
Time delay until Suspend
Table 5.6
Symbol Vdet0 - td(E-A) Vccmin
Voltage Detection 0 Circuit Electrical Characteristics
Parameter Voltage detection level Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(2) MCU operating voltage minimum value VCA25 = 1, VCC = 5.0 V Condition Standard Min. 2.2 - - 2.2 Typ. 2.3 0.9 - - Max. 2.4 - 300 - Unit V A s V
NOTES: 1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0.
Table 5.7
Symbol Vdet1 - - td(E-A)
Voltage Detection 1 Circuit Electrical Characteristics
Parameter Voltage detection level(4) Voltage monitor 1 interrupt request generation time(2) VCA26 = 1, VCC = 5.0 V Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) Condition Standard Min. 2.70 - - - Typ. 2.85 40 0.6 - Max. 3.00 - - 100 Unit V s A s
NOTES: 1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. 4. This parameter shows the voltage detection level when the power supply drops. The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 V.
Table 5.8
Symbol Vdet2 - - td(E-A)
Voltage Detection 2 Circuit Electrical Characteristics
Parameter Voltage detection level Voltage monitor 2 interrupt request generation time(2) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) VCA27 = 1, VCC = 5.0 V Condition Standard Min. 3.3 - - - Typ. 3.6 40 0.6 - Max. 3.9 - - 100 Unit V s A s
NOTES: 1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0.
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.9
Symbol Vpor1 Vpor2 trth
Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Parameter Power-on reset valid voltage(4) Power-on reset or voltage monitor 0 reset valid voltage External power VCC rise gradient(2) Condition Standard Min. - 0 20 Typ. - - - Max. 0.1 Vdet0 - Unit V V mV/msec
NOTES: 1. The measurement condition is Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. This condition (external power VCC rise gradient) does not apply if VCC 1.0 V. 3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. 4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20C Topr 85C, maintain tw(por1) for 3,000 s or more if -40C Topr < -20C.
Vdet0(3) 2.2V External Power VCC Vpor1 tw(por1) Sampling time(1, 2) trth Vpor2 trth
Vdet0(3)
Internal reset signal ("L" valid) 1 x 32 fOCO-S 1 x 32 fOCO-S
NOTES: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (2.2 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details. 3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.
Figure 5.3
Reset Circuit Electrical Characteristics
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 29 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.10
Symbol fOCO40M
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter High-speed on-chip oscillator frequency temperature * supply voltage dependence Condition VCC = 4.75 V to 5.25 V 0C Topr 60C(2) VCC = 3.0 V to 5.5 V -20C Topr 85C(2) VCC = 3.0 V to 5.5 V -40C Topr 85C(2) VCC = 2.7 V to 5.5 V -20C Topr 85C(2) VCC = 2.7 V to 5.5 V -40C Topr 85C(2) VCC = 2.2 V to 5.5 V -20C Topr 85C(3) VCC = 2.2 V to 5.5 V -40C Topr 85C(3) VCC = 5.0 V 10% -20C Topr 85C(2) VCC = 5.0 V 10% -40C Topr 85C(2) Standard Min. 39.2 38.8 38.4 38 37.6 35.2 34 38.8 38.4 08h(3) Adjust FRA1 register (value after reset) to -1 VCC = 5.0 V, Topr = 25C - - - Typ. 40 40 40 40 40 40 40 40 40 - +0.3 10 400 Max. 40.8 41.2 41.6 42 42.4 44.8 46 40.8 40.8 F7h(3) - 100 - Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz - MHz s A
- - - -
Value in FRA1 register after reset Oscillation frequency adjustment unit of highspeed on-chip oscillator Oscillation stability time Self power consumption at oscillation
NOTES: 1. VCC = 2.2 to 5.5 V, Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. These standard values show when the FRA1 register value after reset is assumed. 3. These standard values show when the corrected value of the FRA6 register is written to the FRA1 register.
Table 5.11
Symbol fOCO-S - -
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation VCC = 5.0 V, Topr = 25C Condition Standard Min. 30 - - Typ. 125 10 15 Max. 250 100 - Unit kHz s A
NOTE: 1. VCC = 2.2 to 5.5 V, Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.
Table 5.12
Symbol td(P-R) td(R-S)
Power Supply Circuit Timing Characteristics
Parameter Time for internal power supply stabilization during power-on(2) STOP exit time(3) Condition Standard Min. 1 - Typ. - - Max. 2000 150 Unit s s
NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.13
Symbol tSUCYC tHI tLO tRISE tFALL tSU tH tLEAD tLAG tOD tSA tOR
Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Parameter SSCK clock cycle time SSCK clock "H" width SSCK clock "L" width SSCK clock rising time SSCK clock falling time Master Slave Master Slave Conditions Standard Min. 4 0.4 0.4 - - - - 100 1 1tCYC + 50 1tCYC + 50 - 2.7 V VCC 5.5 V 2.2 V VCC < 2.7 V SSI slave out open time 2.7 V VCC 5.5 V 2.2 V VCC < 2.7 V - - - - Typ. - - - - - - - - - - - - - - - - Max. - 0.6 0.6 1 1 1 1 - - - - 1 1.5tCYC + 100 1.5tCYC + 200 1.5tCYC + 100 1.5tCYC + 200 tCYC(2) tSUCYC tSUCYC tCYC(2) s tCYC(2) s ns tCYC(2) ns ns tCYC(2) ns ns ns ns Unit
SSO, SSI data input setup time SSO, SSI data input hold time SCS setup time SCS hold time SSI slave access time Slave Slave
SSO, SSI data output delay time
NOTES: 1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. 1tCYC = 1/f1(s)
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIH or VOH tHI tFALL tRISE
SSCK (output) (CPOS = 1)
tLO tHI
SSCK (output) (CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIH or VOH tHI tFALL tRISE
SSCK (output) (CPOS = 1)
tLO tHI
SSCK (output) (CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 32 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH tLEAD tHI tFALL tRISE tLAG
SSCK (input) (CPOS = 1)
tLO tHI
SSCK (input) (CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0 SCS (input)
VIH or VOH VIH or VOH tLEAD tHI tFALL tRISE tLAG
SSCK (input) (CPOS = 1)
tLO tHI
SSCK (input) (CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
tHI VIH or VOH
SSCK
VIH or VOH tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
Figure 5.6
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode)
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.14
Symbol tSCL tSCLH tSCLL tsf tSP tBUF tSTAH tSTAS tSTOP tSDAS tSDAH
Timing Requirements of I2C bus Interface (1)
Parameter SCL input cycle time SCL input "H" width SCL input "L" width SCL, SDA input fall time SCL, SDA input spike pulse rejection time SDA input bus-free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time Condition Standard Typ. (2) - 12tCYC + 600 Min. 3tCYC + 300(2)
- - - - - - - - - -
Unit Max. -
- -
ns ns ns ns ns ns ns ns ns ns ns
5tCYC + 500(2) - - 5tCYC(2) 3tCYC(2) 3tCYC(2) 3tCYC(2) 1tCYC + 20(2) 0
300 1tCYC(2) -
- - - - -
NOTES: 1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. 1tCYC = 1/f1(s)
VIH
SDA
VIL tBUF tSTAH tSCLH tSTAS tSP tSTOP
SCL
P(2) S(1) tsf tSCLL tSCL Sr(3) tsr tSDAH tSDAS P(2)
NOTES: 1. Start condition 2. Stop condition 3. Retransmit start condition
Figure 5.7
I/O Timing of I2C bus Interface
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.15
Symbol VOH
Electrical Characteristics (1) [VCC = 5 V]
Parameter Condition IOH = -5 mA IOH = -200 A Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 5 mA IOL = 200 A Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW Standard Min. Typ. VCC - 2.0 - VCC - 0.5 - VCC - 2.0 - VCC - 2.0 - VCC - 2.0 - VCC - 2.0 - - - - - - - - - - - - - 0.1 0.5 Max. VCC VCC VCC VCC VCC VCC 2.0 0.45 2.0 2.0 2.0 2.0 - Unit V V V V V V V V V V V V V
Output "H" voltage Except P1_0 to P1_7, XOUT P1_0 to P1_7 XOUT
IOH = -20 mA IOH = -5 mA IOH = -1 mA IOH = -500 A
VOL
Output "L" voltage Except P1_0 to P1_7, XOUT P1_0 to P1_7 XOUT
IOL = 20 mA IOL = 5 mA IOL = 1 mA IOL = 500 A
VT+-VT-
Hysteresis
INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO RESET VI = 5 V, VCC = 5 V VI = 0 V, VCC = 5 V VI = 0 V, VCC = 5 V
0.1
- -
1.0
- -
-
V
A A k M
IIH IIL RPULLUP RfXIN RfXCIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback XIN resistance Feedback XCIN resistance RAM hold voltage
5.0
-5.0
30 -
-
50 1.0 18
-
167 -
- -
M V
During stop mode
1.8
NOTE: 1. VCC = 4.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 20 MHz, unless otherwise specified.
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.16
Electrical Characteristics (2) [Vcc = 5 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition
XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8
Symbol ICC
Power supply High-speed current clock mode (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS
Min. -
Standard Typ. Max. 10 17
Unit mA
-
9
15
mA
-
6
-
mA
-
5
-
mA
-
4
-
mA
-
2.5
-
mA
High-speed on-chip oscillator mode
XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8
-
10
15
mA
-
4
-
mA
-
5.5
10
mA
-
2.5
-
mA
Low-speed on-chip oscillator mode Low-speed clock mode
XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1
-
130
300
A
-
130
300
A
-
30
-
A
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.17
Electrical Characteristics (3) [Vcc = 5 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition
XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1
Symbol ICC
Power supply Wait mode current (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS
Min. -
Standard Typ. Max. 25 75
Unit
A
-
23
60
A
-
4.0
-
A
-
2.2
-
A
Stop mode
XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0
-
0.8
3.0
A
-
1.2
-
A
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25C) [VCC = 5 V] Table 5.18
Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width
5. Electrical Characteristics
XIN Input, XCIN Input
Parameter Standard Min. Max. 50 - 25 - 25 - 14 - 7 - 7 - Unit ns ns ns s s s
tC(XIN) tWH(XIN)
VCC = 5 V
XIN input
tWL(XIN)
Figure 5.8
XIN Input and XCIN Input Timing Diagram when VCC = 5 V
Table 5.19
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 100 - 40 - 40 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 5 V
TRAIO input
tWL(TRAIO)
Figure 5.9
TRAIO Input Timing Diagram when VCC = 5 V
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.20
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 1
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 200 - 100 - 100 - - 50 0 - 50 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 5 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 or 1
Figure 5.10
Serial Interface Timing Diagram when VCC = 5 V
Table 5.21
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0, 1, 3) Input
Parameter INTi input "H" width INTi input "L" width Standard Min. Max. (1) - 250 250(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 5.11
External Interrupt INTi Input Timing Diagram when VCC = 5 V
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.22
Symbol VOH
Electrical Characteristics (3) [VCC = 3 V]
Parameter Condition IOH = -1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOH = -5 mA IOH = -1 mA Standard Min. Typ. VCC - 0.5 - VCC - 0.5 VCC - 0.5
- - - - - - - - -
Output "H" voltage
Except P1_0 to P1_7, XOUT P1_0 to P1_7
Max. VCC VCC VCC VCC VCC 0.5 0.5 0.5 0.5 0.5
-
Unit V V V V V V V V V V V
XOUT
IOH = -0.1 mA VCC - 0.5 IOH = -50 A VCC - 0.5
-
VOL
Output "L" voltage
Except P1_0 to P1_7, XOUT P1_0 to P1_7
IOL = 5 mA IOL = 1 mA IOL = 0.1 mA IOL = 50 A
- - - -
XOUT
VT+-VT-
Hysteresis
INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO RESET VI = 3 V, VCC = 3 V VI = 0 V, VCC = 3 V VI = 0 V, VCC = 3 V XIN XCIN During stop mode
0.1
0.3
0.1
- -
0.4
- -
-
V
A A k M M V
IIH IIL RPULLUP RfXIN RfXCIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance Feedback resistance RAM hold voltage
4.0
-4.0
66 - - 1.8
160 3.0 18 -
500 - - -
NOTE: 1. VCC =2.7 to 3.3 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 10 MHz, unless otherwise specified.
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.23
Electrical Characteristics (4) [Vcc = 3 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. - Standard Typ. Max. 6 - Unit mA
Symbol ICC
Power supply current High-speed (VCC = 2.7 to 3.3 V) clock mode Single-chip mode, output pins are open, other pins are VSS
-
2
-
mA
High-speed on-chip oscillator mode
-
5
9
mA
-
2
-
mA
Low-speed on-chip oscillator mode Low-speed clock mode
-
130
300
A
-
130
300
A
-
30
-
A
Wait mode
-
25
70
A
-
23
55
A
-
3.8
-
A
-
2.0
-
A
Stop mode
-
0.7
3.0
A
-
1.1
-
A
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R8C/26 Group, R8C/27 Group
Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25C) [VCC = 3 V] Table 5.24
Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width
5. Electrical Characteristics
XIN Input, XCIN Input
Parameter Standard Min. Max. 100 - 40 - 40 - 14 - 7 - 7 - Unit ns ns ns s s s
tC(XIN) tWH(XIN)
VCC = 3 V
XIN input
tWL(XIN)
Figure 5.12
XIN Input and XCIN Input Timing Diagram when VCC = 3 V
Table 5.25
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 300 - 120 - 120 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 3 V
TRAIO input
tWL(TRAIO)
Figure 5.13
TRAIO Input Timing Diagram when VCC = 3 V
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.26
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 1
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi Input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 300 - 150 - 150 - - 80 0 - 70 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 3 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 or 1
Figure 5.14
Serial Interface Timing Diagram when VCC = 3 V
Table 5.27
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0, 1, 3) Input
Parameter INTi input "H" width INTi input "L" width Standard Min. Max. (1) - 380 380(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 5.15
External Interrupt INTi Input Timing Diagram when VCC = 3 V
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.28
Symbol VOH
Electrical Characteristics (5) [VCC = 2.2 V]
Parameter Condition IOH = -1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOH = -2 mA IOH = -1 mA Standard Min. Typ. VCC - 0.5 - VCC - 0.5 VCC - 0.5
- - - - - - - - -
Output "H" voltage
Except P1_0 to P1_7, XOUT P1_0 to P1_7
Max. VCC VCC VCC VCC VCC 0.5 0.5 0.5 0.5 0.5
-
Unit V V V V V V V V V V V
XOUT
IOH = -0.1 mA VCC - 0.5 IOH = -50 A VCC - 0.5
-
VOL
Output "L" voltage
Except P1_0 to P1_7, XOUT P1_0 to P1_7
IOL = 2 mA IOL = 1 mA IOL = 0.1 mA IOL = 50 A
- - - -
XOUT
VT+-VT-
Hysteresis
INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO RESET VI = 2.2 V VI = 0 V VI = 0 V XIN XCIN During stop mode
0.05
0.3
0.05
- -
0.15
- -
-
V
A A k M M V
IIH IIL RPULLUP RfXIN RfXCIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance Feedback resistance RAM hold voltage
4.0
-4.0
100 - - 1.8
200 5 35 -
600 - - -
NOTE: 1. VCC = 2.2 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 5 MHz, unless otherwise specified.
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.29
Electrical Characteristics (6) [Vcc = 2.2 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. - Standard Typ. Max. 3.5 - Unit mA
Symbol ICC
Power supply current High-speed (VCC = 2.2 to 2.7 V) clock mode Single-chip mode, output pins are open, other pins are VSS
-
1.5
-
mA
High-speed on-chip oscillator mode
-
3.5
-
mA
-
1.5
-
mA
Low-speed on-chip oscillator mode Low-speed clock mode
-
100
230
A
-
100
230
A
-
25
-
A
Wait mode
-
22
60
A
-
20
55
A
-
3.0
-
A
-
1.8
-
A
Stop mode
-
0.7
3.0
A
-
1.1
-
A
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Timing requirements (Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25C) [VCC = 2.2 V] Table 5.30
Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width
XIN Input, XCIN Input
Parameter Standard Min. Max. 200 - 90 - 90 - 14 - 7 - 7 - Unit ns ns ns s s s
tC(XIN) tWH(XIN)
VCC = 2.2 V
XIN input
tWL(XIN)
Figure 5.16
XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V
Table 5.31
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 500 - 200 - 200 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 2.2 V
TRAIO input
tWL(TRAIO)
Figure 5.17
TRAIO Input Timing Diagram when VCC = 2.2 V
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.32
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 1
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 800 - 400 - 400 - - 200 0 - 150 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 2.2 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 or 1
Figure 5.18
Serial Interface Timing Diagram when VCC = 2.2 V
Table 5.33
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0, 1, 3) Input
Parameter INTi input "H" width INTi input "L" width Standard Min. Max. - 1000(1) 1000(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 5.19
External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
5.2
J, K Version
J and K versions are under development. Specifications may be changed without prior notice.
Table 5.34
Symbol VCC/AVCC VI VO Pd Topr Tstg
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Condition Rated Value -0.3 to 6.5 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 300 125 -40 to 85 (J version) / -40 to 125 (K version) -65 to 150 Unit V V V mW mW C
C
-40 C Topr 85 C
85 C Topr 125 C
Table 5.35
Symbol VCC/AVCC VSS/AVSS VIH VIL IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(peak) IOL(avg) f(XIN)
Recommended Operating Conditions
Parameter Supply voltage Supply voltage Input "H" voltage Input "L" voltage Peak sum output Sum of all pins "H" current IOH(peak) Peak output "H" current Average output "H" current Peak sum output Sum of all pins "L" currents IOL(peak) Peak output "L" currents Average output "L" current XIN clock input oscillation frequency Conditions Min. 2.7 - 0.8 VCC 0 -
- - - - -
Standard Typ. - 0 - - -
- - - - - - - - - - -
Max. 5.5 - VCC 0.2 VCC -60 -10 -5 60 10 5 20 16 10 20 16 10 -
Unit V V V V mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz kHz
-
System clock
OCD2 = 0 XlN clock selected
OCD2 = 1 On-chip oscillator clock selected
3.0 V VCC 5.5 V (other than K version) 3.0 V VCC 5.5 V (K version) 2.7 V VCC < 3.0 V 3.0 V VCC 5.5 V (other than K version) 3.0 V VCC 5.5 V (K version) 2.7 V VCC < 3.0 V FRA01 = 0 Low-speed on-chip oscillator clock selected FRA01 = 1 High-speed on-chip oscillator clock selected (other than K version) FRA01 = 1 High-speed on-chip oscillator clock selected
0 0 0 0 0 0 -
125
-
-
20
MHz
-
-
10
MHz
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. The typical values when average output current is 100 ms.
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.36
Symbol
- -
A/D Converter Characteristics
Parameter Resolution Absolute accuracy Conditions Vref = AVCC AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 3.3 V AD = 10 MHz, Vref = AVCC = 3.3 V Vref = AVCC AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 5.0 V Min. - - - - - 10 3.3 2.8 2.7 0 0.25 1 Standard Typ. Max. - 10 - 3 - 2 - 5 - 2 - 40 - - - - - AVCC - AVCC
- -
Unit Bits LSB LSB LSB LSB k s s V V MHz MHz
10-bit mode 8-bit mode 10-bit mode 8-bit mode
Rladder tconv Vref VIA
-
Resistor ladder Conversion time 10-bit mode 8-bit mode Reference voltage Analog input voltage(2) A/D operating Without sample and hold clock frequency With sample and hold
10 10
NOTES: 1. AVCC = 2.7 to 5.5 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode.
P0 P1 P3 P4 P5 30pF
Figure 5.20
Ports P0, P1, and P3 to P5 Timing Measurement Circuit
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 50 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.37
Symbol
- - -
Flash Memory (Program ROM) Electrical Characteristics
Parameter Program/erase endurance(2) Byte program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(7) Ambient temperature = 55C Conditions R8C/26 Group R8C/27 Group Min. 100(3) 1,000(3) - - - 650 0
-
Standard Typ. -
-
Max. -
-
Unit times times
s
td(SR-SUS)
- - - - - - -
50 0.4 -
- - - - - - -
400 9 97+CPU clock x 6 cycles -
-
s
s s
ns
s
2.7 2.7 0 20
3+CPU clock x 4 cycles 5.5 5.5 60 -
V V C year
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.38
Symbol
- - - - -
Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Parameter Program/erase endurance(2) Byte program time (program/erase endurance 1,000 times) Byte program time (program/erase endurance > 1,000 times) Block erase time (program/erase endurance 1,000 times) Block erase time (program/erase endurance > 1,000 times) Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(9) Ambient temperature = 55 C Conditions Min. 10,000(3) -
- - - -
Standard Typ. - 50 65 0.2 0.3
- - - - - - - -
Max. - 400
-
Unit times
s s
9
-
s s
s s
td(SR-SUS)
- - - - - - -
650 0
-
97+CPU clock x 6 cycles -
-
ns
s
2.7 2.7 -40 20
3+CPU clock x 4 cycles 5.5 5.5 85(8) -
V V C year
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times is the same as that in program ROM. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 8. 125C for K version. 9. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Suspend request (maskable interrupt request)
FMR46
Fixed time Clock-dependent time Access restart
td(SR-SUS)
Figure 5.21
Time delay until Suspend
Table 5.39
Symbol Vdet1
-
Voltage Detection 1 Circuit Electrical Characteristics
Parameter Voltage detection level(2, 4) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) MCU operating voltage minimum value Condition Min. 2.70
- -
Standard Typ. Max. 2.85 3.0 0.6 -
- -
Unit V
A s
VCA26 = 1, VCC = 5.0 V
td(E-A) Vccmin
100
-
2.70
V
NOTES: 1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40 to 85C (J version) / -40 to 125C (K version). 2. Hold Vdet2 > Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. 4. This parameter shows the voltage detection level when the power supply drops. The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 V.
Table 5.40
Symbol Vdet2
- -
Voltage Detection 2 Circuit Electrical Characteristics
Parameter Voltage detection level(2) Voltage monitor 2 interrupt request generation Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(4) time(3) VCA27 = 1, VCC = 5.0 V Condition Min. 3.3
- - -
Standard Typ. Max. 3.6 3.9 40 0.6 -
- -
Unit V
s A s
td(E-A)
100
NOTES: 1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40 to 85C (J version) / -40 to 125C (K version). 2. Hold Vdet2 > Vdet1. 3. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 4. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0.
Rev.1.30 May 25, 2007 REJ03B0168-0130
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R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.41
Symbol Vpor1 Vpor2 trth
Power-on Reset Circuit, Voltage Monitor 1 Reset Electrical Characteristics(3)
Parameter Power-on reset valid voltage(4) Power-on reset or voltage monitor 1 reset valid voltage External power VCC rise gradient(2) Condition Min. - 0 20 Standard Typ. -
- -
Max. 0.1 Vdet1
-
Unit V V mV/msec
NOTES: 1. The measurement condition is Topr = -40 to 85C (N version) / -40 to 125C (D version), unless otherwise specified. 2. This condition (external power VCC rise gradient) does not apply if VCC 1.0 V. 3. To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. 4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20C Topr 125C, maintain tw(por1) for 3,000 s or more if -40C Topr < -20C.
Vdet1(3) External power VCC Vpor1 tw(por1) Sampling time(1, 2) trth 2.7V trth Vpor2
Vdet1(3)
Internal reset signal ("L" valid) 1 x 32 fOCO-S 1 x 32 fOCO-S
NOTES: 1. When using the voltage monitor 1 digital filter, ensure that the voltage is within the MCU operation voltage range (2.7 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details. 3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.
Figure 5.22
Reset Circuit Electrical Characteristics
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 54 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.42
Symbol fOCO40M
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter High-speed on-chip oscillator frequency temperature * supply voltage dependence Condition VCC = 4.75 V to 5.25 V 0C Topr 60C(2) VCC = 3.0 V to 5.5 V -20C Topr 85C(2) VCC = 3.0 V to 5.5 V -40C Topr 85C(2) VCC = 3.0 V to 5.5 V -40C Topr 125C(2) VCC = 2.7 V to 5.5 V -40C Topr 125C(2) Adjust FRA1 register (value after reset) to -1 VCC = 5.0 V, Topr = 25C Min. 39.2 38.8 38.4 38 37.6 08h -
- -
Standard Typ. 40 40 40 40 40
- +0.3
Max. 40.8 41.2 41.6 42 42.4 F7h - 100 -
Unit MHz MHz MHz MHz MHz
- MHz s A
- - - -
Value in FRA1 register after reset Oscillation frequency adjustment unit of highspeed on-chip oscillator Oscillation stability time Self power consumption at oscillation
10 400
NOTES: 1. VCC = 2.7 to 5.5 V, Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. These standard values show when the FRA1 register value after reset is assumed.
Table 5.43
Symbol fOCO-S - -
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation Condition Min. 40 - - Standard Typ. 125 10 15 Max. 250 100 - Unit kHz s A
VCC = 5.0 V, Topr = 25C
NOTE: 1. VCC = 2.7 to 5.5 V, Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified.
Table 5.44
Symbol td(P-R) td(R-S)
Power Supply Circuit Timing Characteristics
Parameter Time for internal power supply stabilization during power-on(2) STOP exit time(3) Condition Min. 1
-
Standard Typ. Max. - 2000
-
Unit
s s
150
NOTES: 1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 55 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.45
Symbol tSUCYC tHI tLO tRISE tFALL tSU tH tLEAD tLAG tOD tSA tOR
Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Parameter SSCK clock cycle time SSCK clock "H" width SSCK clock "L" width SSCK clock rising time SSCK clock falling time Conditions Min. 4 0.4 0.4 -
- - - 100 1
Standard Typ. -
- - - - - - - - - - - - -
Unit Max. - 0.6 0.6 1 1 1 1
- - - -
tCYC(2) tSUCYC tSUCYC tCYC(2) s tCYC(2) s ns tCYC(2) ns ns tCYC(2) ns ns
Master Slave Master
Slave SSO, SSI data input setup time SSO, SSI data input hold time SCS setup time Slave Slave
1tCYC + 50 1tCYC + 50
- - -
SCS hold time SSO, SSI data output delay time SSI slave access time SSI slave out open time
1 1.5tCYC + 100 1.5tCYC + 100
NOTES: 1. VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. 1tCYC = 1/f1(s)
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 56 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIH or VOH tHI tFALL tRISE
SSCK (output) (CPOS = 1)
tLO tHI
SSCK (output) (CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIH or VOH tHI tFALL tRISE
SSCK (output) (CPOS = 1)
tLO tHI
SSCK (output) (CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
CPHS, CPOS: Bits in SSMR register
Figure 5.23
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 57 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH tLEAD tHI tFALL tRISE tLAG
SSCK (input) (CPOS = 1)
tLO tHI
SSCK (input) (CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0 SCS (input)
VIH or VOH VIH or VOH tLEAD tHI tFALL tRISE tLAG
SSCK (input) (CPOS = 1)
tLO tHI
SSCK (input) (CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.24
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 58 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
tHI VIH or VOH
SSCK
VIH or VOH tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
Figure 5.25
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode)
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 59 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.46
Symbol tSCL tSCLH tSCLL tsf tSP tBUF tSTAH tSTAS tSTOP tSDAS tSDAH
Timing Requirements of I2C bus Interface (1)
Parameter SCL input cycle time SCL input "H" width SCL input "L" width SCL, SDA input fall time SCL, SDA input spike pulse rejection time SDA input bus-free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time Condition Standard Typ. (2) - 12tCYC + 600 Min. 3tCYC + 300(2)
- - - - - - - - - -
Unit Max. -
- -
ns ns ns ns ns ns ns ns ns ns ns
5tCYC + 500(2) - - 5tCYC(2) 3tCYC(2) 3tCYC(2) 3tCYC(2) 1tCYC + 20(2) 0
300 1tCYC(2) -
- - - - -
NOTES: 1. VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. 1tCYC = 1/f1(s)
VIH
SDA
VIL tBUF tSTAH tSCLH tSTAS tSP tSTOP
SCL
P(2) S(1) tsf tSCLL tSCL Sr(3) tsr tSDAH tSDAS P(2)
NOTES: 1. Start condition 2. Stop condition 3. Retransmit start condition
Figure 5.26
I/O Timing of I2C bus Interface
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 60 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.47
Symbol VOH
Electrical Characteristics (1) [VCC = 5 V]
Parameter Condition IOH = -5 mA IOH = -200 A Drive capacity HIGH Drive capacity LOW IOL = 5 mA IOL = 200 A Drive capacity HIGH Drive capacity LOW Standard Min. Typ. VCC - 2.0 - VCC - 0.3 - VCC - 2.0 - VCC - 2.0 - - - - - - - - - 0.1 0.5 Max. VCC VCC VCC VCC 2.0 0.45 2.0 2.0 - Unit V V V V V V V V V
Output "H" voltage
Except XOUT XOUT
IOH = -1 mA IOH = -500 A
VOL
Output "L" voltage
Except XOUT XOUT
IOL = 1 mA IOL = 500 A
VT+-VT-
Hysteresis
INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO RESET VI = 5 V, VCC = 5V VI = 0 V, VCC = 5V VI = 0 V, VCC = 5V XIN During stop mode
0.1
- -
1.0
- -
-
V
A A k M
IIH IIL RPULLUP RfXIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance RAM hold voltage
30 - 2.0
50 1.0
-
5.0 -5.0 167 -
-
V
NOTE: 1. VCC = 4.2 to 5.5 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), f(XIN) = 20 MHz, unless otherwise specified.
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 61 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.48
Electrical Characteristics (2) [Vcc = 5 V] (Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified.)
Parameter Condition
XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8
Symbol ICC
Power supply High-speed current clock mode (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS
Min. -
Standard Typ. Max. 10 17
Unit mA
-
9
15
mA
-
6
-
mA
-
5
-
mA
-
4
-
mA
-
2.5
-
mA
High-speed on-chip oscillator mode
XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz (J version) Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz (J version) Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8
-
10
15
mA
-
4
-
mA
-
5.5
10
mA
-
2.5
-
mA
Low-speed on-chip oscillator mode Wait mode
XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1
-
130
300
A
-
25
75
A
-
23
60
A
Stop mode
XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 125C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0
-
0.8
3.0
A
-
1.2
-
A
-
4.0
-
A
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 62 of 69
R8C/26 Group, R8C/27 Group
Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25C) [VCC = 5 V] Table 5.49
Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN input cycle time XIN input "H" width XIN input "L" width
5. Electrical Characteristics
XIN Input
Parameter Standard Min. Max. 50 - 25 - 25 - Unit ns ns ns
tC(XIN) tWH(XIN)
VCC = 5 V
XIN input
tWL(XIN)
Figure 5.27
XIN Input Timing Diagram when VCC = 5 V
Table 5.50
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 100 - 40 - 40 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 5 V
TRAIO input
tWL(TRAIO)
Figure 5.28
TRAIO Input Timing Diagram when VCC = 5 V
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 63 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.51
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 1
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 200 - 100 - 100 - - 50 0 - 50 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 5 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 or 1
Figure 5.29
Serial Interface Timing Diagram when VCC = 5 V
Table 5.52
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0, 1, 3) Input
Parameter INTi input "H" width INTi input "L" width Standard Min. Max. (1) - 250 250(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 5.30
External Interrupt INTi Input Timing Diagram when VCC = 5 V
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 64 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.53
Symbol VOH
Electrical Characteristics (3) [VCC = 3 V]
Parameter Condition IOH = -1 mA Drive capacity HIGH Drive capacity LOW IOL = 1 mA Drive capacity HIGH Drive capacity LOW Standard Min. Typ. VCC - 0.5 - VCC - 0.5 - VCC - 0.5
- - - - -
Output "H" voltage
Except XOUT XOUT
IOH = -0.1 mA IOH = -50 A
Max. VCC VCC VCC 0.5 0.5 0.5
-
Unit V V V V V V V
VOL
Output "L" voltage
Except XOUT XOUT
IOL = 0.1 mA IOL = 50 A
- -
VT+-VT-
Hysteresis
INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0,CLK1, SSI, SCL, SDA, SSO RESET VI = 3 V, VCC = 3V VI = 0 V, VCC = 3V VI = 0 V, VCC = 3V XIN During stop mode
0.1
0.3
0.1
- -
0.4
- -
-
V
A A k M V
IIH IIL RPULLUP RfXIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance RAM hold voltage
66 - 2.0
160 3.0 -
4.0 -4.0 500 - -
NOTE: 1. VCC =2.7 to 3.3 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), f(XIN) = 10 MHz, unless otherwise specified.
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 65 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.54
Electrical Characteristics (4) [Vcc = 3 V] (Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified.)
Parameter Condition XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 125C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. - Standard Typ. Max. 6 - Unit mA
Symbol ICC
Power supply current High-speed (VCC = 2.7 to 3.3 V) clock mode Single-chip mode, output pins are open, other pins are VSS
-
2
-
mA
High-speed on-chip oscillator mode
-
5
9
mA
-
2
-
mA
Low-speed on-chip oscillator mode Wait mode
-
130
300
A
-
25
70
A
-
23
55
A
Stop mode
-
0.7
3.0
A
-
1.1
-
A
-
3.8
-
A
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 66 of 69
R8C/26 Group, R8C/27 Group
Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25C) [VCC = 3 V] Table 5.55
Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN input cycle time XIN input "H" width XIN input "L" width
5. Electrical Characteristics
XIN Input
Parameter Standard Min. Max. 100 - 40 - 40 - Unit ns ns ns
tC(XIN) tWH(XIN)
VCC = 3 V
XIN input
tWL(XIN)
Figure 5.31
XIN Input Timing Diagram when VCC = 3 V
Table 5.56
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 300 - 120 - 120 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 3 V
TRAIO input
tWL(TRAIO)
Figure 5.32
TRAIO Input Timing Diagram when VCC = 3 V
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 67 of 69
R8C/26 Group, R8C/27 Group
5. Electrical Characteristics
Table 5.57
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 1
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi Input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 300 - 150 - 150 - - 80 0 - 70 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 3 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 or 1
Figure 5.33
Serial Interface Timing Diagram when VCC = 3 V
Table 5.58
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0, 1, 3) Input
Parameter INTi input "H" width INTi input "L" width Standard Min. Max. (1) - 380 380(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 5.34
External Interrupt INTi Input Timing Diagram when VCC = 3 V
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 68 of 69
R8C/26 Group, R8C/27 Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website.
JEITA Package Code P-LQFP32-7x7-0.80 RENESAS Code PLQP0032GB-A Previous Code 32P6U-A MASS[Typ.] 0.2g
HD *1
D
24
17 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
25
16
HE
E
c1
*2
c
Reference Dimension in Millimeters Symbol
Terminal cross section 32
1 ZD Index mark
8
ZE
9
A2
A
F
A1
L L1
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
y e
*3
Detail F bp x
Min Nom Max 6.9 7.0 7.1 6.9 7.0 7.1 1.4 8.8 9.0 9.2 8.8 9.0 9.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0 8 0.8 0.20 0.10 0.7 0.7 0.3 0.5 0.7 1.0
Rev.1.30 May 25, 2007 REJ03B0168-0130
Page 69 of 69
c
REVISION HISTORY REVISION HISTORY
Rev. 0.10 0.20 Date Nov 14, 2005 Feb 06, 2006
R8C/26 Group, R8C/27 Group Datasheet R8C/26 Group, R8C/27 Group Datasheet
Description
Page
-
Summary First edition issued Table 1.1 Functions and Specifications for R8C/26Group and Table 1.2 Functions and Specifications for R8C/27 Group; Minimum instruction execution time and Supply voltage revised Table 1.6 Pin Name Information by Pin Number; "XOUT" "XOUT/XCOUT" and "XIN" "XIN/XCIN" revised Table 4.4 SFR Information (4); 00FEh: "DRR" "P1DRR" revised Table 4.5 SFR Information (5); -0119h: "Timer RE Minute Data Register / Compare Register" "Timer RE Minute Data Register / Compare Data Register" -011Ah: "Timer RE Time Data Register" "Timer RE Hour Data Register" -011Bh: "Timer RE Day Data Register" "Timer RE Day of Week Data Register" revised
2, 3
9 18 19
22 to 45 5. Electrical Characteristics added 1.00 Nov 08, 2006 All pages "Preliminary" deleted 2 3 4 5 6 7 9 15 Table 1.1 revised Table 1.2 revised Figure 1.1 revised Table 1.3 revised Table 1.4 revised Figure 1.4 revised Table 1.6 revised Table 4.1; * 001Ch: "00h" "00h, 10000000b" revised * 000Fh: "000XXXXXb" "00X11111b" revised * 0029h: "High-Speed On-Chip Oscillator Control Register 4, FRA4, When shipping" added * 002Bh: "High-Speed On-Chip Oscillator Control Register 6, FRA6, When shipping" added * 0032h: "00h, 01000000b" "00h, 00100000b" revised * 0038h: "00001000b, 01001001b" "0000X000b, 0100X001b" revised * NOTE3 and 4 revised; NOTE6 added Table 4.4; * 00E0h, 00E1h, 00E5h, 00E8h, 00E9h: "XXh" "00h" revised * 00FDh: "XX00000000b" "00h" revised Table 5.2 revised Figure 5.1 title revised Table 5.4 revised Table 5.5 revised Figure 5.2 title revised and Table 5.7 NOTE4 added
18
22 23 24 25 26
A-1
REVISION HISTORY
R8C/26 Group, R8C/27 Group Datasheet
Description
Rev. 1.00
Date Nov 08, 2006
Page 27 28 34 35 36 39 40 44 47 Table 5.10, Table 5.11 revised Table 5.15 revised Table 5.16 revised Table 5.17 revised Table 5.22 revised Table 5.23 revised Table 5.29 revised
Summary Table 5.9, Figure 5.3 revised and Table 5.10 deleted
Package Dimensions; "Diagrams showing the latest...website." added 1 "J and K versions are under development...notice." added 1.1 revised Table 1.1 revised Table 1.2 revised Figure 1.1 NOTE3 added Table 1.3, Figure 1.2 revised Table 1.4, Figure 1.3 revised Figure 1.4 NOTE3 added Table 1.5 revised Table 1.6 NOTE2 added Figure 3.1 revised Figure 3.2 revised Table 4.1; "0000h to 003Fh" "0000h to 002Fh" revised * NOTE3 added Table 4.2; "0040h to 007Fh" "0030h to 007Fh" revised * 0032h, 0036h: "After reset" is revised * 0038h: NOTE revised * NOTES 2, 5, 6 revised and NOTE 7, 8 added Table 4.5 NOTE2 added Table 5.10 revised Table 4.4 NOTE2 added Table 1.1 revised Table 1.2 revised Table 1.3 revised Figure 1.2 revised Table 1.4 revised Figure 1.3 revised Figure 1.4 NOTE4 added Figure 3.1 part number revised A-2
1.10
Nov 29, 2006
All pages "J, K version" added 1 2 3 4 5 6 7 8 9 13 14 15 16
19 28 1.20 1.30 Jan 17, 2007 May 25, 2007 18 2 3 5 6 7 8 9 15
48 to 66 5.2 J, K Version added
REVISION HISTORY
R8C/26 Group, R8C/27 Group Datasheet
Description
Rev. 1.30
Date May 25, 2007
Page 16 30 53 55 Figure 3.2 part number revised Table 5.10 revised Table 5.39 NOTE4 added Table 5.42 revised
Summary
A-3
Sales Strategic Planning Div.
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
(c) 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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